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HaiLa: Senior Rf And Mixed Signal Asic Design Engineer


This is a Full-time position in Laval, QC posted July 17, 2021.

Are you looking for the next challenge?Do you want to become part of the technical team of a successful start-up?Then this is the place for you!HaiLa https://www.Haila.Io/HaiLa is a Canadian fabless semiconductor startup headquartered in Montreal, Quebec.Founded in 2017, HaiLa’s Mission is to enable the widespread adoption of IoT by reducing the total cost of deployment through leveraging ultra-low power backscatter communications using existing Wi-Fi infrastructure.VISIONHaiLa is helping to build the world of the future, where billions of battery-free sensors monitor machines, living spaces, and environments to help decision makers reduce waste and increase efficiency.

We envision a world where sensors can last forever and are dedicated to bringing this vision to reality.By pioneering the adoption of our patented Radioless™ Wi-Fi compatible technology, HaiLa is positioned to become the world leader in ultra-low power Wi-Fi, enabling every industry to leverage this sustainable technology to globally reduce our carbon footprint.Position: Senior RF and mixed signal ASIC Design Engineer (Montreal office-based position).In this role you will:Develop RF, analog/mixed-signal circuitry concepts.Design and verify/debug RF, analog/mixed-signal ICs from product definition through to mass production.Work closely and collaborate with systems and product definition engineers, internal digital designers and 3rd party contractors (for layout, fabrication, and test) to implement the complete ASIC solution.Support IC validation and characterization efforts.Principal Duties and Responsibilities:Analog RF and mixed signal design and simulation to meet parametric and functional requirements.Resolve performance, area, power and system cost tradeoffs to optimize system architecture.Implement modules in hardware design languages such as System Verilog and Catapult HLS.Design tests and functional models using System-C, Python, and System VerilogComplete test plan reviews and coverage-driven constrained-random verificationMake significant contributions to silicon debug and analysis efforts.Qualifications:5+ years of ASIC design experience (RF, Analog, and/or Mixed Signal).Considerable top-level IC design experience and good understanding of analog/mixed-signal design flows (Cadence, Mentor, Synopsys, etc.)Experience with the evaluation and integration of 3rd party vendor IPs.3+ years of experience in chip validation and PCB bring up.5+ years of experience in C/C++ and Python or Matlab.VHDL and Verilog and experience for digital design and verification.Experience with GNU/Linux tools and TCL, Perl, or other scripting languagesExperience with test automation on Windows or Linux platforms.Comprehensive knowledge of IC design flows and excellent problem solving and debugging skills.Strong communication (written and verbal), organizational and interpersonal skills.Experience with high volume IC manufacturing is a plus.Education: MSc.

or Ph.D.

in Electrical or Computer EngineeringWork Experience: 5+ years’ experience in ASIC design, verification, characterization and test.Seniority level: Mid-Senior levelEmployment type: Full-timeJob function: EngineeringIndustries: Semiconductors and Computer HardwareIf this job description sounds like (or close to) you, we encourage you to apply today!Powered by JazzHRIvhzwz72EX